SK Hynix develops new DDR5 modules with multiplexing to double its speed

Sk Hynix Develops New Ddr5 Modules With Multiplexing To Double Its Speed
Sk Hynix Develops New Ddr5 Modules With Multiplexing To Double Its Speed

Together with Intel and Renesas, SK Hynix has developed a new reminiscence module entry know-how referred to as Combined Row Multiplexing (MCR). mixed rank multiplexer). Typically reminiscence modules which have two rows of chips accessible non-simultaneously due to the 64-byte connection to the processor, or 72-byte error correcting code (ECC). What MCR permits is simultaneous entry to each rows, successfully doubling the switch charge between RAM and CPU.

Multiplexing is the merging right into a single information stream of knowledge from two or extra sources. That makes the connection to the CPU have to be 128 bytes to deal with the 64 bytes of each rows concurrently, so this is not going to be accessible for present Intel processors however for the following Xeon. In follow it really works like two RAM modules in a single. In the picture beneath, the reference to a “data buffer” is the multiplexer.


Two rows are sometimes applied within the modules to permit double the traditional capability. But that has an impact on the reminiscence controller, which stresses it and due to this fact doesn’t permit it to attain speeds as excessive as if single-chip modules have been used, except they’re particularly good motherboards. In DDR5 the normal double row is a foul concept, not less than for now, and this MCR would come to clear up the issue.

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The result’s that the speed is virtually doubled, going from the standard 4800 Gb/s to 8000 Gb/s with out requiring specifically screened chips to obtain these speeds. Here we’re speaking about bandwidth and never in regards to the working frequency of the chips, which from the data I assume will probably be DDR5 at 4000 MHz. But since in follow you’re creating two DDR5 modules in a single, the “added speed » turns into «8000 MHz».

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